(1) Field of the Invention
This invention discloses a method to identify problem machines causing excursion in semiconductor manufacturing, and, more particularly, a method that recognizes and uses a process material's grouping patterns to distinguish the machines that are most probably faulty for excursion analysis in semiconductor manufacturing.
(2) Description of the Related Art
In semiconductor manufacturing, an excursion is a departure from the expected result of a particular process step. The majority of excursions are machine-related. The ability to identify problem machines accurately during excursion is important such that these machines can be stopped in a timely manner to contain further propagation of the problem. Wafer lots process through hundreds of processing steps in a wafer fab. Each process step may comprise more than one machine and some machines may be used for multiple processing steps. The huge number of process steps and combinations of machines makes the identification of the problem machine a challenging task.
The most common method for identification of faulty machines in a wafer fab is the well-known ANOVA test. To ensure minimum accuracy of this method, data from a large quantity of excursion material must be collected. This is because this method requires a large amount of data to determine the statistical difference between machines. Another commercially available excursion analysis tool is Yield Mine. This tool also needs a great deal of data to generate reasonable decision tree results as disclosed in U.S. Pat. No. 6,470,229 to Wang et al. Since all wafer fabs strive to start the excursion analysis at the earliest time possible, there is a need for a method that is able to identify problem machines based on a minimum number of wafer lots so as to speed up the excursion analysis.
Prior art patent documents U.S. Pat. No. 6,901,340 to Pasadyn et al, U.S. Pat. No. 6,701,204 to Nicholson, U.S. Pat. No. 6,580,960 to Nicholson, U.S. Pat. No. 6,944,561 to Tseng et al, U.S. Pat. No. 6,885,950 to Mitsutake et al, U.S. Pat. No. 6,826,735 to Ono et al, U.S. Pat. No. 5,991,699 to Kulkarmi et al, and U.S. Pat. No. 5,665,609 to Mori relate to methods for detection of defects for improvement of production yield. Among these prior art, U.S. Pat. Nos. 6,901,340, 6,701,204 and 6,580,960 appear to be closely related to the present invention. U.S. Pat. No. 6,901,340 to Pasadyn et al discloses a method for distinguishing between sources of process variation. This method employs a characteristic thread matrix derived from process parameters such as film thickness and critical dimensions for differentiating the sources of process variation. U.S. Pat. Nos. 6,701,204 and 6,580,960, both to Nicholson, relate to a method for finding an operation and tool combination that causes integrated failure in semiconductor manufacturing. This method involves calculating the cumulative value of bad wafer lots for each tool and the tool with largest maximum cumulative value is most likely to be defective.
None of these prior art documents appear to show a method that is able to identify machines based on their grouping patterns with a minimum of two processed wafer lots.